What is it?

The AD6642 is an 11-bit, 200 MSPS Dual channel intermediate frequency (IF) Receiver specifically designed to support telecommunications applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADC) and Noise Shaping Requantizer (NSR) digital blocks. Each ADC output is connected internally to a NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist region.

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185Msps, the AD6642 can achieve up to 75.5dBFs SNR for a 40MHz bandwidth in the 22% mode and up to 73.7dBFs SNR for a 60MHz bandwidth in the 33% mode.

With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11-bits. The AD6642 can achieve up to 66.5dBFs SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital pre-distortion observation path where wider bandwidths are desired.

How is it used?

Communications, Diversity radio and smart antenna (MIMO) systems, Multimode digital receivers (3G), WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA, I/Q demodulation systems, General-purpose software radios

What are the key features and customer benefits?

* 11-bit 200MSPS output data rate per channel

* Integrated Noise Shaping Requantizer (NSR)

* Performance with NSR enabled:

  * SNR = 75.5 dBFS in 40MHz band to 70MHz @ 185MSPS

  * SNR = 73.7 dBFs in 60MHz band to 70MHz @ 185MSPS

* Performance with NSR disabled:

* SNR = 66.5 dBFS to 70 MHz @ 185MSPS

* SFDR = 85 dBc to 70 MHz @ 185MSPS

* Low power: 600mW @ 185MSPS

* 1.8 V analog supply operation

* 1.8 V LVDS (ANSI-644 levels) output

* Integer 1-to-8 input clock divider

* IF sampling frequencies to 250 MHz

* Internal ADC voltage reference

* 1.75Vp-p default analog input range

* 1.4Vp-p to 2Vp-p SPI programmable input range

* ADC clock duty cycle stabilizer

* 95 dB channel isolation/crosstalk

* Serial port control

* User-configurable, built-in self-test (BIST) capability

* Energy-saving power-down modes

End Market:

Comms - Broadband; Comms - Other; Comms - WireLess